1. Field of the Invention
The present disclosure generally relates to the field of fabricating integrated circuits, and, more particularly, to forming electronic fuses for providing device-internal programming capabilities in complex integrated circuits.
2. Description of the Related Art
In modern integrated circuits, a very high number of individual circuit elements, such as field effect transistors in the form of CMOS, NMOS, PMOS elements, resistors, capacitors and the like are formed on a single chip area. Typically, feature sizes of these circuit elements are steadily decreasing with the introduction of every new circuit generation to provide currently available integrated circuits with an improved degree of performance in terms of speed and/or power consumption. A reduction in size of transistors is an important aspect in steadily improving device performance of complex integrated circuits, such as CPUs. The reduction in size is commonly associated with an increased switching speed, thereby enhancing signal processing performance. In addition to the large number of transistor elements, a plurality of passive circuit elements, such as capacitors, resistors and the like, are typically formed in integrated circuits that are used for a plurality of purposes, such as for decoupling.
Due to the decreased dimensions of circuit elements, not only the performance of the individual transistor elements may be increased, but also their packing density may be improved, thereby providing the potential for incorporating increased functionality into a given chip area. For this reason, highly complex circuits have been developed, which may include different types of circuits, such as analog circuits, digital circuits and the like, thereby providing entire systems on a single chip (SoC). Furthermore, in sophisticated microcontroller devices, an increasing amount of storage capacity may be provided on chip with the CPU core, thereby also significantly enhancing the overall performance of modern computer devices.
In modern integrated circuits, minimal features sizes have now reached approximately 50 nm and less, thereby providing the possibility of incorporating various functional circuit portions at a given chip area, wherein, however, the various circuit portions may have a significantly different performance, for instance with respect to lifetime, reliability and the like. For example, the operating speed of a digital circuit portion, such as a CPU core and the like, may depend on the configuration of the individual transistor elements and also on the characteristics of the metallization system, which may include a plurality of stacked metallization layers so as to comply with a required complex circuit layout. Thus, highly sophisticated manufacturing techniques may be required in order to provide the minimum critical feature sizes of the speed-critical circuit components. For example, sophisticated digital circuitry may be used on the basis of field effect transistors which represent circuit components in which conductivity of a channel region is controlled on the basis of a gate electrode that is separated from the channel region by a thin dielectric material. Performance of the individual field effect transistors is determined, among other things, by the capability of the transistor to switch from a high impedance state into a low impedance state at high speeds, wherein, also, a sufficiently high current may be driven in the low impedance state. This drive current capability is determined, among other things, by the length of the conductive channel that forms in the channel region upon application of an appropriate control voltage to the gate electrode. For this reason, and in view of ever increasing the overall packing density of sophisticated semiconductor devices, the channel length and thus the length of the gate electrode is continuously being reduced, which in turn may require an appropriate adaptation of the capacitive coupling of the gate electrode to the channel region. Consequently, the thickness of the gate dielectric material may also have to be reduced in order to maintain controllability of the conductive channel at a desired high level. However, the shrinkage of the gate dielectric thickness may be associated with an exponential increase of the leakage currents, which may directly channel through the thin gate dielectric material, thereby contributing to enhanced power consumption and thus waste heat, which may contribute to sophisticated conditions during operation of the semiconductor device. Moreover, charge carriers may be injected into the gate dielectric material and may also contribute to a significant degradation of transistor characteristics, such as threshold voltage of the transistors, thereby also contributing to variability of the transistor characteristics over the lifetime of the product. Consequently, reliability and performance of certain sophisticated circuit portions may be determined by material characteristics and process techniques for forming highly sophisticated circuit elements, while other circuit portions may include less critical devices which may thus provide a different behavior over the lifetime compared to critical circuit portions. Consequently, the combination of the various circuit portions in a single semiconductor device may result in a significant different behavior with respect to performance and reliability, wherein the variations of the overall manufacturing process flow may also contribute to a further discrepancy between the various circuit portions. For these reasons, for complex integrated circuits, frequently additional mechanisms may be implemented to allow the circuit itself to adapt performance of certain circuit portions to comply with performance of other circuit portions, for instance after completing the manufacturing process and/or during use of the semiconductor device, for instance when certain critical circuit portions may no longer comply with corresponding performance criteria, thereby requiring an adaptation of certain circuit portions, such as re-adjusting an internal voltage supply, resetting overall circuit speed and the like.
For this purpose, so-called electronic fuses or e-fuses may be provided in the semiconductor devices, which may represent electronic switches that may be activated once in order to provide a desired circuit adaptation. Hence the electronic fuses may be considered as having a high impedance state, which may typically also represent a “programmed” state, and may have a low impedance state, typically representing a non-programmed state of the electronic fuse. Since these electronic fuses may have a significant influence on the overall behavior of the entire integrated circuit, a reliable detection of the non-programmed and the programmed state may have to be guaranteed, which may have to be accomplished on the basis of appropriately designed logic circuitry. Furthermore, since typically these electronic fuses may be actuated once over the lifetime of the semiconductor device under consideration, a corresponding programming activity may have to ensure that a desired programmed state of the electronic fuse is reliably generated in order to provide well-defined conditions for the further operational lifetime of the device. However, with the continuous shrinkage of critical device dimensions in sophisticated semiconductor devices, the reliability of programming corresponding electronic fuses may require tightly set margins for the corresponding voltages used to program the electronic fuses, which may not be compatible with the overall specifications of the semiconductor devices or may at least have a severe influence on the flexibility of operating the device.
With reference to FIGS. 1a-1b, a typical electronic fuse in a sophisticated semiconductor device will now be described in order to more clearly set forth the difficulties in providing electronic fuses in advanced semiconductor devices.
FIG. 1a schematically illustrates a top view of a portion of a semiconductor device 150 which may represent any semiconductor device including sophisticated digital circuitry, such as a CPU core, a controller for graphic applications, memory areas and the like. The semiconductor device 150 may thus comprise a circuit portion 160, which may represent a sophisticated transistor element, such as a field effect transistor having a gate length of 50 nm and less, as previously discussed. Furthermore, the device 150 comprises an electronic fuse 100 that may represent a one-time programmable electronic switch, which may be converted from a low impedance state into a high impedance state upon a current pulse generated by applying an appropriate programming voltage to the electronic fuse 100. As illustrated, the fuse 100 comprises a first contact area 101 and a second contact area 102 and an intermediate region 103, provided in the form of a conductive line, which represents the actual fuse element which may alter its impedance state upon connecting the contact areas 101 and 102 with an appropriate voltage source. Typically, the contact areas 101, 102 and the conductive line 103 are formed of an appropriate electrode material, which may also be used for forming corresponding gate electrode structures of field effect transistors, such as is provided in the portion 160. For example, polysilicon in combination with a metal silicide are frequently used materials for forming the electronic fuse 100. Moreover, as illustrated, each of the contact areas 101, 102 may be connected to corresponding contact elements that are formed in a contact level of the device 150, as will be described in more detail with reference to FIG. 1b. 
FIG. 1b schematically illustrates a cross-sectional view of the device 150 along the line Ib of FIG. 1a. As illustrated, the device 150 comprises a substrate 151, such as a silicon substrate and the like, above which is formed a layer 152, which may represent a semiconductor layer or an insulating material, depending on the position of the electronic fuse 100 within the semiconductor device 150. Furthermore, when the material 152 represents a semiconductor region, an insulating material 153 may be provided, for instance on the basis of a material as may also be used as a gate dielectric material for forming field effect transistors. Moreover, a contact level 120 is formed above the layer 152 so as to enclose the electronic fuse 100 and other circuit elements, such as transistors and the like. Typically, the contact level comprises a dielectric material 122 in combination with an etch stop material 123, such as silicon dioxide and silicon nitride, respectively, in which are formed the contact elements 121 that usually comprise a conductive material such as tungsten, possibly in combination with a conductive barrier material (not shown), such as titanium nitride and the like.
The semiconductor device 150 may be formed on the basis of well-established process techniques in which sophisticated circuit elements such as gate electrodes of field effect transistors and the like may be formed on the basis of critical dimensions of 50 nm and less. For this purpose, an appropriate gate electrode material in combination with a gate dielectric material may be provided and may be patterned on the basis of sophisticated lithography and etch techniques, wherein the contact areas 101, 102 and the region 103 may also be patterned. For example, the conductive line 103 may have a similar geometric configuration compared to gate electrode structures. That is, a width 103W (FIG. 1a) may correspond to the gate length of critical transistor elements, while a length 103L may be several hundred nanometers, depending on the overall configuration. It should be appreciated that, similarly as is the case for transistor elements, the electronic fuse 100 is also to be designed in view of not unduly consuming valuable die area in the device 150. Furthermore, in view of programmability of the fuse 100, that is, of the region 103, it is preferable to provide a minimum cross-sectional area so as to allow a significant modification of the electrical behavior of the region 103 upon applying a sufficiently high current flowing through the region 103. Consequently, the region 103 may be designed in accordance with the corresponding design rules for the device under consideration.
In a further advanced manufacturing stage, that is, patterning the gate electrode structures and thus the contact areas 101, 102 and the region 103, and after forming appropriate drain and source areas for transistor elements, typically the conductivity of semiconductor regions may be increased, for instance by forming a metal silicide in corresponding drain and source areas and gate electrodes, thereby also forming a metal silicide 104 in the contact areas 101, 102 and the region 103. This may be accomplished on the basis of well-established process techniques. It should be appreciated that, during the corresponding manufacturing process, respective sidewalls spacers 105 may also have been formed, which may typically be used for defining corresponding dopant profiles in transistor areas and act as a mask during the silicidation process. Thereafter, the contact level 120 may be formed on the basis of well-established process techniques including the deposition of the materials 123 and 122 and patterning the same in order to obtain appropriate contact openings, which are subsequently filled with conductive material, such as tungsten and the like. Next, a plurality of metallization layers (not shown) are formed, which may provide the wiring fabric for the circuit elements and also for the electronic fuse 100 in accordance with the overall circuit layout.
When operating the device 150 and programming the electronic fuse 100, a sufficiently high voltage is to be applied between the contact areas 101 and 102 in order to generate a sufficient high current density, which may result in a permanent modification in order to blow the fuse 100. For example, in this case, the per se negative effect of electromigration may be efficiently used to induce a current-driven material diffusion in the line 103, which may result in a significant modification of the electrical performance, i.e., a corresponding high impedance state may be achieved due to the “degradation” of the line 103. Electromigration is a well-known effect which may occur in conductive lines, typically metal-containing lines, when current density is very high so that the flow of electrons may cause a directed “diffusion” of ion cores, thereby increasingly transporting material along the electron flow direction. Thus, the corresponding line may increasingly suffer from a depletion of material in the vicinity of the cathode, while material may be deposited at or next to the line in the vicinity of the anode of the fuse 100. As previously discussed, a reliable distinction between a non-programmed state and a programmed state may require a corresponding significant modification of line 103, which may require significant voltages and may also require appropriately designed contact areas 101, 102 and an appropriate number of contact elements 121 connecting thereto in order to provide the required current drive capability for effecting a “blowing” of line 103. Thus, an appropriate tightly set “programming voltage window” may be required for sophisticated devices in order to obtain a high difference between the low impedance state and the high impedance state. Moreover, the corresponding margins for the programming voltage may also have to take account of any process-related fluctuations during the formation of the fuse 100, thereby requiring more tightly set programming voltages. As previously discussed, a corresponding required degree of reliability in detecting the programmed state may require sufficiently high programming voltages, which may not be compatible with the supply voltages used for sophisticated devices.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.